PRAM is an attractive and important model for designers of parallel algorithms. Why?

1. It is natural: the number of operations executed per one cycle on p processors is at most p.
2. It is strong: any processor can read or write any shared memory cell in unit time.
3. It is simple: it abstracts from any communication or synchronization overhead, which makes the complexity and correctness analysis of PRAM algorithms easier. Therefore,
4. It can be used as a benchmark: If a problem has no feasible/efficient solution on PRAM, it has no feasible/efficient solution on any parallel machine.
5. It is useful: it is an idealization of existing (and nowaday more and more abundant) shared memory parallel machines.

The PRAM corresponds intuitively to the programmers' view of a parallel computer: it ignores lower level architectural constraints, and details, such as memory access contention and overhead, synchronization overhead, interconnection network throughput, connectivity, speed limits and link bandwidths, etc.

Constrained PRAM models

1. Bounded number of shared memory cells. This may be called a small memory PRAM. If the input data set exceeds the capacity of the shared memory, the input and/or output values can be distributed evenly among the processors.
2. Bounded size of a machine word and/or memory cell. This parameter is usually called word size of PRAM.
3. Bounded number of processors. This may be called a small PRAM. If the number of threads of execution is higher, processors may interleave several threads.
4. Constraints on simultaneous access to shared memory cells: handling access conflicts.

Limiting the amount of PRAM shared memory corresponds to restricting the amount of information that can be communicated between processors in one step. For example, a distributed memory machine with processors interconnected by a shared bus can be modeled as a PRAM with one shared memory cell.